1. Field of the Invention
The present invention relates generally to an output stage having low power-bouncing characteristics for use in electronic devices, and more particularly, to such low power or ground bouncing characteristics due to current discharge from a capacitive load when the output is switching.
2. Description of Related Art
A ground bouncing phenomenon is a voltage ground Vss fluctuation induced by switching of the outputs of an electronic device. The bouncing is exacerbated by having multiple outputs with simultaneous switching and may cause malfunction of circuits having Vss' as a reference ground. FIG. 1 depicts a typical device circuit with only one detailed output stage shown coupled to a capacitive load. A typical electronic device, such as an integrated circuit (IC) device, comprises 8, 16, 32 or even 64 output stages. As shown in FIG. 1, the output signal A of circuit 11 is input to the gate terminals of MOS transistors M1 and M2. The source terminal of MOS transistor M1 is coupled to the power supply Vdd through an inductance L3 and the source terminal of MOS transistor M2 is coupled to the ground voltage through an inductance L2. The inductance L2 is associated with the inductance inherently existing on the wiring between the source terminal of M2 and an output pin of the IC package. The output Y is taken at the connection of the drain terminal of M1 and the drain terminal of M2. A capacitance C1 is associated with the load to which the output is coupled and the inductance L1 is a wiring inductance. A voltage Vss' is taken at the source terminal of the transistor M2 to be utilized as a ground reference for the circuit 11. For example, the internal flip-flops of the circuit 11 may need a reliable and predictable ground reference Vss' for accurate operation. When output signal Y is not switching, or not changing state, no current is flowing through the inductance L2 and the voltage of Vss' is equal to the GND. However, as the output signal Y is switching from high to low in response to the stage change of signal A, a current I is quickly discharging from the capacitive load C1 through inductance L1, MOS transistor M2 and inductance L2 to GND. The instantaneous value of the current I is equal to C1*dV/dt. The instantaneous value of the Vss induced is, therefore, equal to L2*dI/dt. The voltage induced on the source terminal of transistor M2 results in a ground voltage bouncing of Vss', and is known as a ground bouncing phenomenon in the art. The voltage induced on Vss' will be substantial when multiple outputs are switching at the same time. For instance, as sixteen outputs switch from high to low voltage at the same time, the voltage change of Vss' is equal to 16*L2*dI/dt. A significant fluctuation of Vss' beyond a tolerance limit may cause malfunction of any circuits having Vss' as a reference ground.
By a similar mechanism, a power (Vdd') bouncing phenomenon also exists when the output signals are switching.
The power or ground bouncing phenomenon described above is best illustrated by the wave form of the FIG. 3. As the wave forms of the Vdd' and Vss' show, not only is the deviation from the reference voltage severe, but the time required to reach a steady state is long.
Recent relevant art is disclosed in the U.S. patent Application 07/821,965 which was filed on Jan. 16, 1992.